Since the function blocks were developed previously using technology-independent VHDL, they were resynthesized into a technology-dependent structural description using the Altera library. Figure 12 shows the arrangement of the function blocks along with the Altera input and output pads. The resulting logic was then simulated using VIEWSIM prior to layout as shown in Figure 13. A similar command file to that used on the XILINX pre-layout simulation was used here on the Altera pre-layout simulation. Thus, the waveforms for both implementations are similar, and this verifies that both implementations function properly. The only only change required to retarget the design into the Altera Flex10K was the pinout.
The Altera MAX+PlusII software was used to interface the netlist file tothe actual floorplan used inside the Altera part. Figure 14 shows the physical assignment of the CLBs after placement and routing. The MAX+PlusII software also enables the program to be downloaded into the Flex10K part using the JEDEC protocol.
Figure 12: I/O and Internal Components for Altera Flex10K.
Figure 13: Pre-layout Simulation for Altera using VIEWSIM.
Figure 14: Physical Layout for Altera Flex10K.