Debug for fit_fastio_pin_reassign program (iteration 1): I/O delay matrix:- Comb Reg SU Pin Cout Casc Clk N/A 44 N/A 44 N/A N/A Clr N/A 54 N/A 54 N/A N/A Pre N/A 54 N/A 54 N/A N/A Ena N/A N/A 32 N/A N/A N/A Ald N/A 54 N/A 54 N/A N/A OE N/A N/A N/A 61 N/A N/A Cin N/A N/A N/A N/A N/A N/A Casc N/A N/A N/A N/A N/A N/A Pin 35 N/A 135 N/A N/A N/A A N/A N/A 25 35 N/A N/A B N/A N/A N/A N/A N/A N/A C N/A N/A N/A N/A N/A N/A D N/A N/A N/A N/A N/A N/A Global clock delay matrix:- Comb Reg SU Pin Cout Casc Clk : N/A 26 52 N/A 38 N/A Clr : N/A 27 N/A N/A 39 N/A Pre : N/A 27 N/A N/A 39 N/A Ena : N/A N/A 22 N/A N/A N/A Ald : N/A 27 N/A N/A 39 N/A OE : N/A N/A N/A N/A N/A N/A Cin : 13 N/A 17 N/A 3 15 Casc: 7 N/A 11 N/A N/A 9 Pin : N/A N/A N/A N/A N/A N/A A : 23 N/A 27 N/A 12 25 B : 23 N/A 27 N/A 12 25 C : 23 N/A 27 N/A N/A 25 D : 18 N/A 22 N/A N/A 20 I/O delay matrix:- Comb Reg SU Pin Cout Casc Clk N/A 44 N/A 44 N/A N/A Clr N/A 54 N/A 54 N/A N/A Pre N/A 54 N/A 54 N/A N/A Ena N/A N/A 32 N/A N/A N/A Ald N/A 54 N/A 54 N/A N/A OE N/A N/A N/A 61 N/A N/A Cin N/A N/A N/A N/A N/A N/A Casc N/A N/A N/A N/A N/A N/A Pin 35 N/A 135 N/A N/A N/A A N/A N/A 25 35 N/A N/A B N/A N/A N/A N/A N/A N/A C N/A N/A N/A N/A N/A N/A D N/A N/A N/A N/A N/A N/A Global clock delay matrix:- Comb Reg SU Pin Cout Casc Clk : N/A 26 52 N/A 38 N/A Clr : N/A 27 N/A N/A 39 N/A Pre : N/A 27 N/A N/A 39 N/A Ena : N/A N/A 22 N/A N/A N/A Ald : N/A 27 N/A N/A 39 N/A OE : N/A N/A N/A N/A N/A N/A Cin : 13 N/A 17 N/A 3 15 Casc: 7 N/A 11 N/A N/A 9 Pin : N/A N/A N/A N/A N/A N/A A : 23 N/A 27 N/A 12 25 B : 23 N/A 27 N/A 12 25 C : 23 N/A 27 N/A N/A 25 D : 18 N/A 22 N/A N/A 20 Threshold are: for Tsu - 10.600000ns and for Tco - 17.700000ns Global Tsu=-1(-1.000000), Tco=-1(-1.000000) Input/output cells: CLK -> 125 : IN q6 -> 96 : OUT q7 -> 97 : OUT START -> 124 : IN Set clique dont_touch: Cell: CLK, rdfbits: d, fast_io bit: 0, periphery: 0,0 Cell: |counter22:7|lpm_counter:lpm_counter_component|f8count:p8c0|:7, rdfbits: 110, fast_io bit: 0, periphery: 0,0 Cell: |counter22:7|lpm_counter:lpm_counter_component|f8count:p8c0|:8, rdfbits: 110, fast_io bit: 0, periphery: 0,0 Cell: q6, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: q7, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: |shiftreg8:11|lpm_shiftreg:lpm_shiftreg_component|dffs0, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |shiftreg8:11|lpm_shiftreg:lpm_shiftreg_component|dffs1, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |shiftreg8:11|lpm_shiftreg:lpm_shiftreg_component|dffs2, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |shiftreg8:11|lpm_shiftreg:lpm_shiftreg_component|dffs3, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |shiftreg8:11|lpm_shiftreg:lpm_shiftreg_component|dffs4, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |shiftreg8:11|lpm_shiftreg:lpm_shiftreg_component|dffs5, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |shiftreg8:11|lpm_shiftreg:lpm_shiftreg_component|dffs6, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |shiftreg8:11|lpm_shiftreg:lpm_shiftreg_component|dffs7, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: START, rdfbits: 5, fast_io bit: 0, periphery: 0,0 Cell: |xor4:10|lpm_xor:lpm_xor_component|xor_cascade0_3~1, rdfbits: 1050, fast_io bit: 0, periphery: 0,0 Virtual pin individual set-up and clock-to-output times: For pin CLK delays are: tsu=-1, tco=-1; For pin q6 delays are: tsu=-1, tco=-1; For pin q7 delays are: tsu=-1, tco=-1; For pin START delays are: tsu=-1, tco=-1; Cells driven by pins |shiftreg8:11|lpm_shiftreg:lpm_shiftreg_component|dffs0 is driven by START |shiftreg8:11|lpm_shiftreg:lpm_shiftreg_component|dffs1 is driven by START |shiftreg8:11|lpm_shiftreg:lpm_shiftreg_component|dffs2 is driven by START |shiftreg8:11|lpm_shiftreg:lpm_shiftreg_component|dffs3 is driven by START |shiftreg8:11|lpm_shiftreg:lpm_shiftreg_component|dffs4 is driven by START |shiftreg8:11|lpm_shiftreg:lpm_shiftreg_component|dffs5 is driven by START |shiftreg8:11|lpm_shiftreg:lpm_shiftreg_component|dffs6 is driven by START |shiftreg8:11|lpm_shiftreg:lpm_shiftreg_component|dffs7 is driven by START Cells driving pins |shiftreg8:11|lpm_shiftreg:lpm_shiftreg_component|dffs6 drives q6 |shiftreg8:11|lpm_shiftreg:lpm_shiftreg_component|dffs7 drives q7 FAST I/O assignement after cleaning up: CLK: fast_io=0 q6: fast_io=0 q7: fast_io=0 START: fast_io=0 Layer-by-layer logic: fast_io=0 Layer 0 CLK, RDF bits: d, lab#=0 q6, RDF bits: 3, lab#=0 q7, RDF bits: 3, lab#=0 START, RDF bits: 5, lab#=0 Layer 1 |shiftreg8:11|lpm_shiftreg:lpm_shiftreg_component|dffs0, RDF bits: 210, lab#=0 |shiftreg8:11|lpm_shiftreg:lpm_shiftreg_component|dffs1, RDF bits: 210, lab#=0 |shiftreg8:11|lpm_shiftreg:lpm_shiftreg_component|dffs2, RDF bits: 210, lab#=0 |shiftreg8:11|lpm_shiftreg:lpm_shiftreg_component|dffs3, RDF bits: 210, lab#=0 |shiftreg8:11|lpm_shiftreg:lpm_shiftreg_component|dffs4, RDF bits: 210, lab#=0 |shiftreg8:11|lpm_shiftreg:lpm_shiftreg_component|dffs5, RDF bits: 210, lab#=0 |shiftreg8:11|lpm_shiftreg:lpm_shiftreg_component|dffs6, RDF bits: 210, lab#=0 |shiftreg8:11|lpm_shiftreg:lpm_shiftreg_component|dffs7, RDF bits: 210, lab#=0 Physical pins available: row: 0, col: -1 RDF: 800003c7 row: 0, col: -1 RDF: 800003c7 row: 0, col: -1 RDF: 800003c7 row: 0, col: -1 RDF: 800003c7 row: 0, col: -1 RDF: 800003c7 row: 0, col: -1 RDF: 800003c7 row: 0, col: -1 RDF: 800003c7 row: 0, col: -1 RDF: 800003c7 row: 1, col: -1 RDF: 800003c7 row: 1, col: -1 RDF: 800003c7 row: 1, col: -1 RDF: 800003c7 row: 1, col: -1 RDF: 800003c7 row: 1, col: -1 RDF: 800003c7 row: 1, col: -1 RDF: 800003c7 row: 1, col: -1 RDF: 800003c7 row: 2, col: -1 RDF: 800003c7 row: 2, col: -1 RDF: 800003c7 row: 2, col: -1 RDF: 800003c7 row: 2, col: -1 RDF: 800003c7 row: 2, col: -1 RDF: 800003c7 row: 2, col: -1 RDF: 800003c7 row: -1, col: 1 RDF: 800003c7 row: -1, col: 3 RDF: 800003c7 row: -1, col: 4 RDF: 800003c7 row: -1, col: 5 RDF: 800003c7 row: -1, col: 6 RDF: 800003c7 row: -1, col: 7 RDF: 800003c7 row: -1, col: 8 RDF: 800003c7 row: -1, col: 9 RDF: 800003c7 row: -1, col: 10 RDF: 800003c7 row: -1, col: 10 RDF: 800003c7 row: -1, col: 11 RDF: 800003c7 row: -1, col: 11 RDF: 800003c7 row: -1, col: -1 RDF: 4600080d row: -1, col: -1 RDF: d row: -1, col: -1 RDF: 4600080d row: -1, col: 12 RDF: 800003c7 row: -1, col: 13 RDF: 800003c7 row: -1, col: 14 RDF: 800003c7 row: -1, col: 15 RDF: 800003c7 row: -1, col: 16 RDF: 800003c7 row: -1, col: 17 RDF: 800003c7 row: -1, col: 17 RDF: 800003c7 row: -1, col: 18 RDF: 800003c7 row: -1, col: 19 RDF: 800003c7 row: -1, col: 20 RDF: 800003c7 row: -1, col: 21 RDF: 800003c7 row: -1, col: 22 RDF: 800003c7 row: -1, col: 23 RDF: 800003c7 row: 2, col: -1 RDF: 800003c7 row: 2, col: -1 RDF: 800003c7 row: 2, col: -1 RDF: 800003c7 row: 2, col: -1 RDF: 800003c7 row: 2, col: -1 RDF: 800003c7 row: 2, col: -1 RDF: 800003c7 row: 2, col: -1 RDF: 800003c7 row: 2, col: -1 RDF: 800003c7 row: 1, col: -1 RDF: 800003c7 row: 1, col: -1 RDF: 800003c7 row: 1, col: -1 RDF: 800003c7 row: 1, col: -1 RDF: 800003c7 row: 1, col: -1 RDF: 800003c7 row: 1, col: -1 RDF: 800003c7 row: 1, col: -1 RDF: 800003c7 95. 14 (INIT_DONE) row: 0, col: -1 RDF: 800003c7 row: 0, col: -1 RDF: 800003c7 row: 0, col: -1 RDF: 800003c7 98. 11 (RDYnBUSY) row: 0, col: -1 RDF: 800003c7 row: 0, col: -1 RDF: 800003c7 row: 0, col: -1 RDF: 800003c7 row: 0, col: -1 RDF: 800003c7 102. 7 (CLKUSR) row: 0, col: -1 RDF: 800003c7 109. 144 (nCS) row: -1, col: 23 RDF: 800003c7 110. 143 (CS) row: -1, col: 23 RDF: 800003c7 111. 142 (nWS) row: -1, col: 22 RDF: 800003c7 112. 141 (nRS) row: -1, col: 21 RDF: 800003c7 row: -1, col: 20 RDF: 800003c7 row: -1, col: 19 RDF: 800003c7 row: -1, col: 18 RDF: 800003c7 row: -1, col: 18 RDF: 800003c7 row: -1, col: 17 RDF: 800003c7 row: -1, col: 16 RDF: 800003c7 row: -1, col: 15 RDF: 800003c7 row: -1, col: 14 RDF: 800003c7 row: -1, col: 13 RDF: 800003c7 125. 128 (DEV_OE) row: -1, col: 12 RDF: 800003c7 row: -1, col: -1 RDF: 4600080d row: -1, col: -1 RDF: d row: -1, col: -1 RDF: 4600080d 131. 122 (DEV_CLRn) row: -1, col: 11 RDF: 800003c7 row: -1, col: 9 RDF: 800003c7 row: -1, col: 8 RDF: 800003c7 row: -1, col: 7 RDF: 800003c7 row: -1, col: 6 RDF: 800003c7 row: -1, col: 5 RDF: 800003c7 137. 116 (DATA7) row: -1, col: 4 RDF: 800003c7 139. 114 (DATA6) row: -1, col: 3 RDF: 800003c7 140. 113 (DATA5) row: -1, col: 2 RDF: 800003c7 141. 112 (DATA4) row: -1, col: 2 RDF: 800003c7 142. 111 (DATA3) row: -1, col: 1 RDF: 800003c7 143. 110 (DATA2) row: -1, col: 0 RDF: 800003c7 144. 109 (DATA1) row: -1, col: 0 RDF: 800003c7 Sorted pins: Pin START: Link strength=128, fast_io=0, group No.=1 Pin q6: Link strength=96, fast_io=0, group No.=1 Pin q7: Link strength=96, fast_io=0, group No.=1 Pin CLK: Link strength=0, fast_io=0, group No.=0 Output pin initial assignments: All the rest pin assignments: Layer-by-layer logic: fast_io=1 Layer 0 CLK, RDF bits: d, lab#=0 q6, RDF bits: 3, lab#=0 q7, RDF bits: 3, lab#=0 START, RDF bits: 5, lab#=0 Layer 1 Logic level 1 allocation.