Project Informationc:\laboratorio\altro\esercitazioni2003\esp_fpga_2(cronometro)\pilota_display.rpt

MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 12/04/2003 14:53:52

Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was unsuccessful




** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir 			    LCs
POF       Device          Pins    Pins     Pins      LCs    % Utilized

pilota_display
      EP1810LC-20          21       14       0   59          No Fit

User Pins:                 21       14       0  



Project Informationc:\laboratorio\altro\esercitazioni2003\esp_fpga_2(cronometro)\pilota_display.rpt

** PROJECT COMPILATION MESSAGES **

Warning: Primitive 'db' is stuck at VCC
Error: Project does not fit in specified device(s)
Error: No fit found, generating Report File

(See individual chip error summaries for additional information)

Project Informationc:\laboratorio\altro\esercitazioni2003\esp_fpga_2(cronometro)\pilota_display.rpt

** AUTO GLOBAL SIGNALS **



INFO: Signal 'CLK' chosen for auto global Clock


Project Informationc:\laboratorio\altro\esercitazioni2003\esp_fpga_2(cronometro)\pilota_display.rpt

** FILE HIERARCHY **



|7445:73|
|7447:65|
|mux5:92|
|mux5:92|lpm_mux:lpm_mux_component|
|mux5:92|lpm_mux:lpm_mux_component|bypassff:sel_latency_ff0|
|mux5:92|lpm_mux:lpm_mux_component|altshift:external_latency_ffs|
|mux5:92|lpm_mux:lpm_mux_component|muxlut:82|
|mux5:92|lpm_mux:lpm_mux_component|muxlut:82|muxlut:42|
|mux5:92|lpm_mux:lpm_mux_component|muxlut:82|muxlut:61|
|mux5:92|lpm_mux:lpm_mux_component|muxlut:102|
|mux5:92|lpm_mux:lpm_mux_component|muxlut:102|muxlut:42|
|mux5:92|lpm_mux:lpm_mux_component|muxlut:102|muxlut:61|
|mux5:92|lpm_mux:lpm_mux_component|muxlut:122|
|mux5:92|lpm_mux:lpm_mux_component|muxlut:122|muxlut:42|
|mux5:92|lpm_mux:lpm_mux_component|muxlut:122|muxlut:61|
|mux5:92|lpm_mux:lpm_mux_component|muxlut:142|
|mux5:92|lpm_mux:lpm_mux_component|muxlut:142|muxlut:42|
|mux5:92|lpm_mux:lpm_mux_component|muxlut:142|muxlut:61|
|counter5:93|
|counter5:93|lpm_counter:lpm_counter_component|
|counter5:93|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|
|counter5:93|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|
|counter5:93|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|addcore:adder0|
|counter5:93|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|altshift:result_ext_latency_ffs|
|counter5:93|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|altshift:carry_ext_latency_ffs|
|counter5:93|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|altshift:oflow_ext_latency_ffs|
|counter5:93|lpm_counter:lpm_counter_component|lpm_constant:scdw|
|counter5:93|lpm_counter:lpm_counter_component|cmpconst:95|
|counter2000:95|
|counter2000:95|lpm_counter:lpm_counter_component|
|counter2000:95|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|
|counter2000:95|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|
|counter2000:95|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|addcore:adder1|
|counter2000:95|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|addcore:adder0|
|counter2000:95|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|altshift:result_ext_latency_ffs|
|counter2000:95|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|altshift:carry_ext_latency_ffs|
|counter2000:95|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|altshift:oflow_ext_latency_ffs|
|counter2000:95|lpm_counter:lpm_counter_component|lpm_constant:scdw|
|counter2000:95|lpm_counter:lpm_counter_component|cmpconst:143|


Device-Specific Information:c:\laboratorio\altro\esercitazioni2003\esp_fpga_2(cronometro)\pilota_display.rpt
pilota_display

***** Logic for device 'pilota_display' contains errors -- see ERROR SUMMARY.




Device: EP1810LC-20

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF



Device-Specific Information:c:\laboratorio\altro\esercitazioni2003\esp_fpga_2(cronometro)\pilota_display.rpt
pilota_display

** ERROR SUMMARY **

Error: Project requires too many (59/48) logic cells
Error: Project requires too many (23/16) global logic cells


Device-Specific Information:c:\laboratorio\altro\esercitazioni2003\esp_fpga_2(cronometro)\pilota_display.rpt
pilota_display

** RESOURCE USAGE **

Logic Array Block     Logic Cells   I/O Pins       

A:     LC1 - LC12     0/12(  0%)   0/12(  0%) 
B:    LC13 - LC24     0/12(  0%)   0/12(  0%) 
C:    LC25 - LC36     0/12(  0%)   0/12(  0%) 
D:    LC37 - LC48     0/12(  0%)   0/12(  0%) 


Total dedicated input pins used:                 0/16     (  0%)
Total I/O pins used:                             0/48     (  0%)
Total logic cells used:                          0/48     (  0%)
Average fan-in:                                  9.61
Total fan-in:                                   567

Total input pins required:                      21
Total output pins required:                     14
Total bidirectional pins required:               0
Total logic cells required:                     59
Total flipflops required:                       17

Synthesized logic cells:                        27/  48   ( 56%)



Device-Specific Information:c:\laboratorio\altro\esercitazioni2003\esp_fpga_2(cronometro)\pilota_display.rpt
pilota_display

** INPUTS **

                                        Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   INP  FBK  OUT  FBK  Name
  ??      -   ??      INPUT  G           0    0    0    0  CLK
  ??      -   ??      INPUT              0    0    0   14  data00
  ??      -   ??      INPUT              0    0    0   14  data01
  ??      -   ??      INPUT              0    0    0   16  data02
  ??      -   ??      INPUT              0    0    0   11  data03
  ??      -   ??      INPUT              0    0    0   12  data10
  ??      -   ??      INPUT              0    0    0   14  data11
  ??      -   ??      INPUT              0    0    0   14  data12
  ??      -   ??      INPUT              0    0    0   11  data13
  ??      -   ??      INPUT              0    0    0   15  data20
  ??      -   ??      INPUT              0    0    0   15  data21
  ??      -   ??      INPUT              0    0    0   18  data22
  ??      -   ??      INPUT              0    0    0   13  data23
  ??      -   ??      INPUT              0    0    0   13  data30
  ??      -   ??      INPUT              0    0    0   14  data31
  ??      -   ??      INPUT              0    0    0   14  data32
  ??      -   ??      INPUT              0    0    0   10  data33
  ??      -   ??      INPUT              0    0    0   14  data40
  ??      -   ??      INPUT              0    0    0   14  data41
  ??      -   ??      INPUT              0    0    0   15  data42
  ??      -   ??      INPUT              0    0    0   11  data43


Code:

g = Global logic cell
s = Synthesized pin or logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.


Device-Specific Information:c:\laboratorio\altro\esercitazioni2003\esp_fpga_2(cronometro)\pilota_display.rpt
pilota_display

** OUTPUTS **

                                        Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   INP  FBK  OUT  FBK  Name
  ??     ??   ??     OUTPUT              0    4    0    0  A1
  ??     ??   ??     OUTPUT              0    4    0    0  A2
  ??     ??   ??     OUTPUT              0    4    0    0  A3
  ??     ??   ??     OUTPUT              0    4    0    0  A4
  ??     ??   ??     OUTPUT              0    4    0    0  A5
  ??     ??   ??     OUTPUT              0    4    0    0  c1k
  ??     ??   ??     OUTPUT              0    0    0    0  db
  ??     ??   ??     OUTPUT              0    8    0    0  OA
  ??     ??   ??     OUTPUT              0    3    0    0  OB
  ??     ??   ??     OUTPUT              0    4    0    0  OC
  ??     ??   ??     OUTPUT              0    5    0    0  OD
  ??     ??   ??     OUTPUT              0    2    0    0  OE
  ??     ??   ??     OUTPUT              0    4    0    0  OF
  ??     ??   ??     OUTPUT              0    4    0    0  OG


Code:

g = Global logic cell
s = Synthesized pin or logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:c:\laboratorio\altro\esercitazioni2003\esp_fpga_2(cronometro)\pilota_display.rpt
pilota_display

** BURIED LOGIC **

                                        Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   INP  FBK  OUT  FBK  Name
   -     ??   ??        TFF              0    4    6   24  |counter5:93|lpm_counter:lpm_counter_component|dffs0
   -     ??   ??        TFF              0    2    6   24  |counter5:93|lpm_counter:lpm_counter_component|dffs1
   -     ??   ??        TFF              0    4    6   27  |counter5:93|lpm_counter:lpm_counter_component|dffs2
   -     ??   ??        TFF              0    5    6    2  |counter5:93|lpm_counter:lpm_counter_component|dffs3
   -     ??   ??       SOFT    s         0    3    0    1  |counter5:93|lpm_counter:lpm_counter_component|~159~1
   -     ??   ??        TFF   +          0    0    0   15  |counter2000:95|lpm_counter:lpm_counter_component|dffs0
   -     ??   ??        TFF   +          0    1    0   14  |counter2000:95|lpm_counter:lpm_counter_component|dffs1
   -     ??   ??        TFF   +          0    2    0   13  |counter2000:95|lpm_counter:lpm_counter_component|dffs2
   -     ??   ??        TFF   +          0    3    0   12  |counter2000:95|lpm_counter:lpm_counter_component|dffs3
   -     ??   ??        TFF   +          0   12    0   10  |counter2000:95|lpm_counter:lpm_counter_component|dffs4
   -     ??   ??        DFF   +          0   12    0   10  |counter2000:95|lpm_counter:lpm_counter_component|dffs5
   -     ??   ??        DFF   +          0   12    0    9  |counter2000:95|lpm_counter:lpm_counter_component|dffs6
   -     ??   ??        DFF   +          0   12    0    9  |counter2000:95|lpm_counter:lpm_counter_component|dffs7
   -     ??   ??        TFF   +          0   11    0    8  |counter2000:95|lpm_counter:lpm_counter_component|dffs8
   -     ??   ??        TFF   +          0   11    0    8  |counter2000:95|lpm_counter:lpm_counter_component|dffs9
   -     ??   ??        TFF   +          0   11    0    8  |counter2000:95|lpm_counter:lpm_counter_component|dffs10
   -     ??   ??        DFF   +          0   12    0    8  |counter2000:95|lpm_counter:lpm_counter_component|dffs11
   -     ??   ??       SOFT              0    7    0    1  |counter2000:95|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|addcore:adder0|result_node5
   -     ??   ??       SOFT    s         0    4    0    4  |counter2000:95|lpm_counter:lpm_counter_component|~305~1
   -     ??   ??       SOFT    s         0    8    0    1  |counter2000:95|lpm_counter:lpm_counter_component|~311~1
   -     ??   ??        DFF   +          0   12    0    4  :105
   -     ??   ??       SOFT    s        20    3    1    0  |7447:65|OA~1 (|7447:65|~81~1)
   -     ??   ??       SOFT    s        19    3    1    0  |7447:65|OA~2 (|7447:65|~81~2)
   -     ??   ??       SOFT    s        12    3    1    0  |7447:65|OA~3 (|7447:65|~81~3)
   -     ??   ??       SOFT    s        14    3    1    0  |7447:65|OA~4 (|7447:65|~81~4)
   -     ??   ??       SOFT    s        12    3    1    0  |7447:65|OA~5 (|7447:65|~81~5)
   -     ??   ??       SOFT    s         4    1    1    0  |7447:65|OA~6 (|7447:65|~81~6)
   -     ??   ??       SOFT    s        15    3    2    0  |7447:65|OB~1 (|7447:65|~82~1)
   -     ??   ??       SOFT    s        11    3    1    0  |7447:65|OB~2 (|7447:65|~82~2)
   -     ??   ??       SOFT    s        20    3    1    0  |7447:65|OB~3 (|7447:65|~82~3)
   -     ??   ??       SOFT    s        10    3    1    0  |7447:65|OB~4 (|7447:65|~82~4)
   -     ??   ??       SOFT    s        10    3    2    0  |7447:65|OC~1 (|7447:65|~83~1)
   -     ??   ??       SOFT    s        14    3    1    0  |7447:65|OC~2 (|7447:65|~83~2)
   -     ??   ??       SOFT    s        12    3    1    0  |7447:65|OC~3 (|7447:65|~83~3)
   -     ??   ??       SOFT    s         3    1    1    0  |7447:65|OC~4 (|7447:65|~83~4)
   -     ??   ??       SOFT    s        15    3    2    0  |7447:65|OD~1 (|7447:65|~84~1)
   -     ??   ??       SOFT    s        10    3    3    0  |7447:65|OD~2 (|7447:65|~84~2)
   -     ??   ??       SOFT    s        14    3    1    0  |7447:65|OD~3 (|7447:65|~84~3)
   -     ??   ??       SOFT    s         7    3    1    0  |7447:65|OD~4 (|7447:65|~84~4)
   -     ??   ??       SOFT    s        10    3    2    0  |7447:65|OE~1 (|7447:65|~85~1)
   -     ??   ??       SOFT    s         5    3    1    0  |7447:65|OE~2 (|7447:65|~85~2)
   -     ??   ??       SOFT    s        16    3    1    0  |7447:65|OF~1 (|7447:65|~86~1)
   -     ??   ??       SOFT    s         4    1    1    0  |7447:65|OF~2 (|7447:65|~86~2)
   -     ??   ??       SOFT    s        12    3    1    0  |7447:65|OG~1 (|7447:65|~87~1)
   -     ??   ??       SOFT    s         3    1    1    0  |7447:65|OG~2 (|7447:65|~87~2)


Code:

g = Global logic cell
s = Synthesized pin or logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:c:\laboratorio\altro\esercitazioni2003\esp_fpga_2(cronometro)\pilota_display.rpt
pilota_display

** EQUATIONS **

CLK      : INPUT;
data00   : INPUT;
data01   : INPUT;
data02   : INPUT;
data03   : INPUT;
data10   : INPUT;
data11   : INPUT;
data12   : INPUT;
data13   : INPUT;
data20   : INPUT;
data21   : INPUT;
data22   : INPUT;
data23   : INPUT;
data30   : INPUT;
data31   : INPUT;
data32   : INPUT;
data33   : INPUT;
data40   : INPUT;
data41   : INPUT;
data42   : INPUT;
data43   : INPUT;

-- Node name is 'A1' 
-- Equation name is 'A1', type is output 
 A1      = LCELL(!_EQ001);
  _EQ001 = !_N015 &  _N016 & !_N017 & !_N018;

-- Node name is 'A2' 
-- Equation name is 'A2', type is output 
 A2      = LCELL(!_EQ002);
  _EQ002 = !_N015 & !_N016 &  _N017 &  _N018;

-- Node name is 'A3' 
-- Equation name is 'A3', type is output 
 A3      = LCELL(!_EQ003);
  _EQ003 = !_N015 & !_N016 &  _N017 & !_N018;

-- Node name is 'A4' 
-- Equation name is 'A4', type is output 
 A4      = LCELL(!_EQ004);
  _EQ004 = !_N015 & !_N016 & !_N017 &  _N018;

-- Node name is 'A5' 
-- Equation name is 'A5', type is output 
 A5      = LCELL(!_EQ005);
  _EQ005 = !_N015 & !_N016 & !_N017 & !_N018;

-- Node name is 'c1k' 
-- Equation name is 'c1k', type is output 
 c1k     = LCELL( _EQ006);
  _EQ006 = !_N015 &  _N016 & !_N017 & !_N018;

-- Node name is 'db' 
-- Equation name is 'db', type is output 
 db      = LCELL( VCC);

-- Node name is 'OA' 
-- Equation name is 'OA', type is output 
 OA      = LCELL( _EQ007);
  _EQ007 = !_N033 & !_N034 & !_N035 & !_N036 & !_N037 & !_N038 & !_N039 & 
             !_N040;

-- Node name is 'OB' 
-- Equation name is 'OB', type is output 
 OB      = LCELL(!_EQ008);
  _EQ008 = !_N041 & !_N042 & !_N043;

-- Node name is 'OC' 
-- Equation name is 'OC', type is output 
 OC      = LCELL( _EQ009);
  _EQ009 = !_N042 & !_N044 & !_N045 & !_N046;

-- Node name is 'OD' 
-- Equation name is 'OD', type is output 
 OD      = LCELL( _EQ010);
  _EQ010 = !_N039 & !_N047 & !_N048 & !_N049 & !_N050;

-- Node name is 'OE' 
-- Equation name is 'OE', type is output 
 OE      = LCELL(!_EQ011);
  _EQ011 = !_N045 & !_N051;

-- Node name is 'OF' 
-- Equation name is 'OF', type is output 
 OF      = LCELL( _EQ012);
  _EQ012 = !_N040 & !_N042 & !_N052 & !_N053;

-- Node name is 'OG' 
-- Equation name is 'OG', type is output 
 OG      = LCELL( _EQ013);
  _EQ013 = !_N049 & !_N054 & !_N055 & !_N056;

-- Node name is '|counter5:93|lpm_counter:lpm_counter_component|dffs0' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_N018', type is buried 
_N018    = TFF(!_EQ014,  _N019,  VCC,  VCC);
  _EQ014 = !_N015 &  _N016 & !_N017 & !_N018;

-- Node name is '|counter5:93|lpm_counter:lpm_counter_component|dffs1' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_N017', type is buried 
_N017    = TFF( _N018,  _N019,  VCC,  VCC);

-- Node name is '|counter5:93|lpm_counter:lpm_counter_component|dffs2' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_N016', type is buried 
_N016    = TFF( _EQ015,  _N019,  VCC,  VCC);
  _EQ015 = !_N015 &  _N016 & !_N017 & !_N018
         #  _N017 &  _N018;

-- Node name is '|counter5:93|lpm_counter:lpm_counter_component|dffs3' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_N015', type is buried 
_N015    = TFF(!_EQ016,  _N019,  VCC,  VCC);
  _EQ016 = !_N015 &  _N016 & !_N017 & !_N018
         # !_N057;

-- Node name is '|counter5:93|lpm_counter:lpm_counter_component|~159~1' from file "lpm_counter.tdf" line 966, column 23
-- Equation name is '_N057', type is buried 
-- synthesized logic cell 
_N057    = LCELL( _EQ017);
  _EQ017 =  _N016 &  _N017 &  _N018;

-- Node name is '|counter2000:95|lpm_counter:lpm_counter_component|dffs0' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_N032', type is buried 
_N032    = TFF( VCC, GLOBAL( CLK),  VCC,  VCC);

-- Node name is '|counter2000:95|lpm_counter:lpm_counter_component|dffs1' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_N031', type is buried 
_N031    = TFF( _N032, GLOBAL( CLK),  VCC,  VCC);

-- Node name is '|counter2000:95|lpm_counter:lpm_counter_component|dffs2' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_N030', type is buried 
_N030    = TFF( _EQ018, GLOBAL( CLK),  VCC,  VCC);
  _EQ018 =  _N031 &  _N032;

-- Node name is '|counter2000:95|lpm_counter:lpm_counter_component|dffs3' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_N029', type is buried 
_N029    = TFF( _EQ019, GLOBAL( CLK),  VCC,  VCC);
  _EQ019 =  _N030 &  _N031 &  _N032;

-- Node name is '|counter2000:95|lpm_counter:lpm_counter_component|dffs4' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_N028', type is buried 
_N028    = TFF(!_EQ020, GLOBAL( CLK),  VCC,  VCC);
  _EQ020 = !_N020 &  _N021 &  _N022 &  _N023 &  _N024 &  _N025 & !_N026 & 
             !_N028 &  _N029 &  _N030 &  _N031 &  _N032
         # !_N059;

-- Node name is '|counter2000:95|lpm_counter:lpm_counter_component|dffs5' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_N026', type is buried 
_N026    = DFF(!_EQ021, GLOBAL( CLK),  VCC,  VCC);
  _EQ021 = !_N020 &  _N021 &  _N022 &  _N023 &  _N024 &  _N025 & !_N026 & 
             !_N028 &  _N029 &  _N030 &  _N031 &  _N032
         # !_N027;

-- Node name is '|counter2000:95|lpm_counter:lpm_counter_component|dffs6' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_N025', type is buried 
_N025    = DFF(!_EQ022, GLOBAL( CLK),  VCC,  VCC);
  _EQ022 = !_N020 &  _N021 &  _N022 &  _N023 &  _N024 &  _N025 & !_N026 & 
             !_N028 &  _N029 &  _N030 &  _N031 &  _N032
         #  _N025 &  _N026 &  _N028 &  _N029 &  _N030 &  _N031 &  _N032
         # !_N025 & !_N026
         # !_N025 & !_N028
         # !_N025 & !_N059;

-- Node name is '|counter2000:95|lpm_counter:lpm_counter_component|dffs7' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_N024', type is buried 
_N024    = DFF(!_EQ023, GLOBAL( CLK),  VCC,  VCC);
  _EQ023 = !_N020 &  _N021 &  _N022 &  _N023 &  _N024 &  _N025 & !_N026 & 
             !_N028 &  _N029 &  _N030 &  _N031 &  _N032
         #  _N024 &  _N025 &  _N026 &  _N028 &  _N029 &  _N030 &  _N031 & 
              _N032
         # !_N024 & !_N025
         # !_N024 & !_N026
         # !_N024 & !_N028
         # !_N024 & !_N059;

-- Node name is '|counter2000:95|lpm_counter:lpm_counter_component|dffs8' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_N023', type is buried 
_N023    = TFF( _EQ024, GLOBAL( CLK),  VCC,  VCC);
  _EQ024 = !_N020 &  _N021 &  _N022 &  _N023 &  _N024 &  _N025 & !_N026 & 
             !_N028 &  _N029 &  _N030 &  _N031 &  _N032
         #  _N024 &  _N025 &  _N026 &  _N028 &  _N029 &  _N030 &  _N031 & 
              _N032;

-- Node name is '|counter2000:95|lpm_counter:lpm_counter_component|dffs9' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_N022', type is buried 
_N022    = TFF( _EQ025, GLOBAL( CLK),  VCC,  VCC);
  _EQ025 = !_N020 &  _N021 &  _N022 &  _N023 &  _N024 &  _N025 & !_N026 & 
             !_N028 &  _N029 &  _N030 &  _N031 &  _N032
         #  _N023 &  _N024 &  _N025 &  _N026 &  _N028 &  _N029 &  _N030 & 
              _N031 &  _N032;

-- Node name is '|counter2000:95|lpm_counter:lpm_counter_component|dffs10' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_N021', type is buried 
_N021    = TFF( _EQ026, GLOBAL( CLK),  VCC,  VCC);
  _EQ026 = !_N020 &  _N021 &  _N022 &  _N023 &  _N024 &  _N025 & !_N026 & 
             !_N028 &  _N029 &  _N030 &  _N031 &  _N032
         #  _N022 &  _N023 &  _N024 &  _N025 &  _N026 &  _N028 &  _N029 & 
              _N030 &  _N031 &  _N032;

-- Node name is '|counter2000:95|lpm_counter:lpm_counter_component|dffs11' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_N020', type is buried 
_N020    = DFF(!_EQ027, GLOBAL( CLK),  VCC,  VCC);
  _EQ027 =  _N020 &  _N021 &  _N022 &  _N023 &  _N024 &  _N025 &  _N026 & 
              _N028 &  _N029 &  _N030 &  _N031 &  _N032
         # !_N020 &  _N021 &  _N022 &  _N023 &  _N024 &  _N025 & !_N026 & 
             !_N028 &  _N029 &  _N030 &  _N031 &  _N032
         # !_N020 & !_N058
         # !_N020 & !_N023
         # !_N020 & !_N022
         # !_N020 & !_N021;

-- Node name is '|counter2000:95|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_N027', type is buried 
_N027    = LCELL( _EQ028);
  _EQ028 = !_N026 &  _N028 &  _N029 &  _N030 &  _N031 &  _N032
         #  _N026 & !_N028
         #  _N026 & !_N059;

-- Node name is '|counter2000:95|lpm_counter:lpm_counter_component|~305~1' from file "lpm_counter.tdf" line 966, column 23
-- Equation name is '_N059', type is buried 
-- synthesized logic cell 
_N059    = LCELL( _EQ029);
  _EQ029 =  _N029 &  _N030 &  _N031 &  _N032;

-- Node name is '|counter2000:95|lpm_counter:lpm_counter_component|~311~1' from file "lpm_counter.tdf" line 966, column 23
-- Equation name is '_N058', type is buried 
-- synthesized logic cell 
_N058    = LCELL( _EQ030);
  _EQ030 =  _N024 &  _N025 &  _N026 &  _N028 &  _N029 &  _N030 &  _N031 & 
              _N032;

-- Node name is '|7447:65|~81~1' = '|7447:65|OA~1' 
-- Equation name is '_N033', type is buried 
-- synthesized logic cell 
_N033    = LCELL( _EQ031);
  _EQ031 = !data20 & !data22 & !data23 & !data30 & !data32 & !data33 & 
             !data40 & !data42 & !data43 &  _N017
         # !data20 & !data21 & !data22 & !data30 & !data31 & !data32 & 
             !data40 & !data41 & !data42 &  _N017
         # !data00 & !data02 & !data03 & !data10 & !data12 & !data13 & 
             !data40 & !data42 & !data43 & !_N017
         # !data00 & !data01 & !data02 & !data10 & !data11 & !data12 & 
             !data40 & !data41 & !data42 & !_N017
         # !data30 & !data32 & !data33 & !data40 & !data42 & !data43 &  _N017 & 
              _N018
         # !data30 & !data31 & !data32 & !data40 & !data41 & !data42 &  _N017 & 
              _N018
         # !data10 & !data12 & !data13 & !data40 & !data42 & !data43 & !_N017 & 
              _N018
         # !data20 & !data22 & !data23 & !data30 & !data32 & !data33 & !_N016 & 
              _N017;

-- Node name is '|7447:65|~81~2' = '|7447:65|OA~2' 
-- Equation name is '_N034', type is buried 
-- synthesized logic cell 
_N034    = LCELL( _EQ032);
  _EQ032 = !data20 & !data22 & !data23 & !data40 & !data42 & !data43 &  _N017 & 
             !_N018
         # !data10 & !data11 & !data12 & !data40 & !data41 & !data42 & !_N017 & 
              _N018
         # !data20 & !data21 & !data22 & !data30 & !data31 & !data32 & !_N016 & 
              _N017
         # !data20 & !data21 & !data22 & !data40 & !data41 & !data42 &  _N017 & 
             !_N018
         # !data00 & !data02 & !data03 & !data10 & !data12 & !data13 & !_N016 & 
             !_N017
         # !data00 & !data02 & !data03 & !data40 & !data42 & !data43 & !_N017 & 
             !_N018
         # !data00 & !data01 & !data02 & !data10 & !data11 & !data12 & !_N016 & 
             !_N017
         # !data00 & !data01 & !data02 & !data40 & !data41 & !data42 & !_N017 & 
             !_N018;

-- Node name is '|7447:65|~81~3' = '|7447:65|OA~3' 
-- Equation name is '_N035', type is buried 
-- synthesized logic cell 
_N035    = LCELL( _EQ033);
  _EQ033 =  data30 &  data32 & !data33 & !_N016 &  _N017 &  _N018
         #  data30 & !data31 &  data33 & !_N016 &  _N017 &  _N018
         #  data31 & !data32 & !data33 & !_N016 &  _N017 &  _N018
         # !data31 & !data32 &  data33 & !_N016 &  _N017 &  _N018
         #  data10 &  data12 & !data13 & !_N016 & !_N017 &  _N018
         #  data20 &  data22 & !data23 & !_N016 &  _N017 & !_N018
         #  data10 & !data11 &  data13 & !_N016 & !_N017 &  _N018
         #  data20 & !data21 &  data23 & !_N016 &  _N017 & !_N018;

-- Node name is '|7447:65|~81~4' = '|7447:65|OA~4' 
-- Equation name is '_N036', type is buried 
-- synthesized logic cell 
_N036    = LCELL( _EQ034);
  _EQ034 = !data30 & !data32 & !data33 & !_N016 &  _N017 &  _N018
         # !data30 & !data31 & !data32 & !_N016 &  _N017 &  _N018
         #  data11 & !data12 & !data13 & !_N016 & !_N017 &  _N018
         #  data21 & !data22 & !data23 & !_N016 &  _N017 & !_N018
         # !data11 & !data12 &  data13 & !_N016 & !_N017 &  _N018
         # !data21 & !data22 &  data23 & !_N016 &  _N017 & !_N018
         #  data00 &  data02 & !data03 & !_N016 & !_N017 & !_N018
         #  data00 & !data01 &  data03 & !_N016 & !_N017 & !_N018;

-- Node name is '|7447:65|~81~5' = '|7447:65|OA~5' 
-- Equation name is '_N037', type is buried 
-- synthesized logic cell 
_N037    = LCELL( _EQ035);
  _EQ035 = !data10 & !data12 & !data13 & !_N016 & !_N017 &  _N018
         # !data20 & !data22 & !data23 & !_N016 &  _N017 & !_N018
         # !data10 & !data11 & !data12 & !_N016 & !_N017 &  _N018
         # !data20 & !data21 & !data22 & !_N016 &  _N017 & !_N018
         #  data01 & !data02 & !data03 & !_N016 & !_N017 & !_N018
         # !data01 & !data02 &  data03 & !_N016 & !_N017 & !_N018
         # !data00 & !data02 & !data03 & !_N016 & !_N017 & !_N018
         # !data00 & !data01 & !data02 & !_N016 & !_N017 & !_N018;

-- Node name is '|7447:65|~81~6' = '|7447:65|OA~6' 
-- Equation name is '_N038', type is buried 
-- synthesized logic cell 
_N038    = LCELL( _EQ036);
  _EQ036 =  data40 &  data42 & !data43 &  _N016
         #  data40 & !data41 &  data43 &  _N016
         #  data41 & !data42 & !data43 &  _N016
         # !data41 & !data42 &  data43 &  _N016
         # !data40 & !data42 & !data43 &  _N016
         # !data40 & !data41 & !data42 &  _N016;

-- Node name is '|7447:65|~82~1' = '|7447:65|OB~1' 
-- Equation name is '_N039', type is buried 
-- synthesized logic cell 
_N039    = LCELL( _EQ037);
  _EQ037 =  data30 &  data31 & !data33 & !_N016 &  _N017 &  _N018
         #  data10 &  data11 & !data13 & !_N016 & !_N017 &  _N018
         #  data20 &  data21 & !data23 & !_N016 &  _N017 & !_N018
         #  data00 &  data01 & !data03 & !_N016 & !_N017 & !_N018
         #  data40 &  data41 & !data43 &  _N016;

-- Node name is '|7447:65|~82~2' = '|7447:65|OB~2' 
-- Equation name is '_N047', type is buried 
-- synthesized logic cell 
_N047    = LCELL( _EQ038);
  _EQ038 =  data20 &  data21 & !data23 &  data30 &  data31 & !data33 & 
              data40 &  data41 & !data43 &  _N017
         #  data30 &  data31 & !data33 &  data40 &  data41 & !data43 &  _N017 & 
              _N018
         #  data20 &  data21 & !data23 &  data30 &  data31 & !data33 & !_N016 & 
              _N017
         #  data20 &  data21 & !data23 &  data40 &  data41 & !data43 &  _N017 & 
             !_N018
         # !data21 & !data22 & !data31 & !data32 &  data40 &  data41 & 
             !data43 &  _N017
         # !data22 & !data23 & !data32 & !data33 &  data40 &  data41 & 
             !data43 &  _N017
         # !data20 & !data21 & !data30 & !data31 &  data40 &  data41 & 
             !data43 &  _N017
         # !data20 & !data21 & !data30 & !data31 & !data40 & !data41 &  _N017;

-- Node name is '|7447:65|~82~3' = '|7447:65|OB~3' 
-- Equation name is '_N048', type is buried 
-- synthesized logic cell 
_N048    = LCELL( _EQ039);
  _EQ039 = !data22 & !data23 & !data32 & !data33 & !data42 & !data43 &  _N017
         # !data00 & !data01 & !data10 & !data11 & !data40 & !data41 & !_N017
         # !data02 & !data03 & !data12 & !data13 & !data42 & !data43 & !_N017
         # !data30 & !data31 & !_N016 &  _N017 &  _N018
         # !data32 & !data33 & !_N016 &  _N017 &  _N018
         # !data10 & !data11 & !_N016 & !_N017 &  _N018
         # !data20 & !data21 & !_N016 &  _N017 & !_N018
         # !data12 & !data13 & !_N016 & !_N017 &  _N018;

-- Node name is '|7447:65|~82~4' = '|7447:65|OB~4' 
-- Equation name is '_N050', type is buried 
-- synthesized logic cell 
_N050    = LCELL( _EQ040);
  _EQ040 = !data22 & !data23 & !_N016 &  _N017 & !_N018
         # !data00 & !data01 & !_N016 & !_N017 & !_N018
         # !data02 & !data03 & !_N016 & !_N017 & !_N018
         # !data40 & !data41 &  _N016
         # !data42 & !data43 &  _N016;

-- Node name is '|7447:65|~83~1' = '|7447:65|OC~1' 
-- Equation name is '_N049', type is buried 
-- synthesized logic cell 
_N049    = LCELL( _EQ041);
  _EQ041 = !data21 & !data22 & !data31 & !data32 & !data41 & !data42 &  _N017
         # !data01 & !data02 & !data11 & !data12 & !data41 & !data42 & !_N017
         # !data31 & !data32 & !_N016 &  _N017 &  _N018
         # !data11 & !data12 & !_N016 & !_N017 &  _N018
         # !data21 & !data22 & !_N016 &  _N017 & !_N018
         # !data01 & !data02 & !_N016 & !_N017 & !_N018
         # !data41 & !data42 &  _N016;

-- Node name is '|7447:65|~83~2' = '|7447:65|OC~2' 
-- Equation name is '_N054', type is buried 
-- synthesized logic cell 
_N054    = LCELL( _EQ042);
  _EQ042 = !data01 & !data03 &  data22 & !data23 & !data41 & !data43 & !_N018
         # !data01 & !data03 &  data20 & !data22 & !data41 & !data43 & !_N018
         # !data31 & !data33 & !data41 & !data42 &  _N017 &  _N018
         # !data21 & !data22 & !data31 & !data33 & !_N016 &  _N017
         # !data21 & !data23 & !data41 & !data42 &  _N017 & !_N018
         # !data11 & !data13 & !data41 & !data42 & !_N017 &  _N018
         # !data01 & !data02 & !data11 & !data13 & !_N016 & !_N017
         # !data01 & !data03 & !data41 & !data42 & !_N017 & !_N018;

-- Node name is '|7447:65|~83~3' = '|7447:65|OC~3' 
-- Equation name is '_N055', type is buried 
-- synthesized logic cell 
_N055    = LCELL( _EQ043);
  _EQ043 =  data32 & !data33 & !_N016 &  _N017 &  _N018
         #  data30 & !data32 & !_N016 &  _N017 &  _N018
         #  data12 & !data13 & !_N016 & !_N017 &  _N018
         #  data22 & !data23 & !_N016 &  _N017 & !_N018
         #  data10 & !data12 & !_N016 & !_N017 &  _N018
         #  data20 & !data22 & !_N016 &  _N017 & !_N018
         #  data02 & !data03 & !_N016 & !_N017 & !_N018
         #  data00 & !data02 & !_N016 & !_N017 & !_N018;

-- Node name is '|7447:65|~83~4' = '|7447:65|OC~4' 
-- Equation name is '_N056', type is buried 
-- synthesized logic cell 
_N056    = LCELL( _EQ044);
  _EQ044 =  data42 & !data43 &  _N016
         #  data40 & !data42 &  _N016;

-- Node name is '|7447:65|~84~1' = '|7447:65|OD~1' 
-- Equation name is '_N040', type is buried 
-- synthesized logic cell 
_N040    = LCELL( _EQ045);
  _EQ045 =  data30 & !data31 &  data32 & !_N016 &  _N017 &  _N018
         #  data10 & !data11 &  data12 & !_N016 & !_N017 &  _N018
         #  data20 & !data21 &  data22 & !_N016 &  _N017 & !_N018
         #  data00 & !data01 &  data02 & !_N016 & !_N017 & !_N018
         #  data40 & !data41 &  data42 &  _N016;

-- Node name is '|7447:65|~84~2' = '|7447:65|OD~2' 
-- Equation name is '_N042', type is buried 
-- synthesized logic cell 
_N042    = LCELL( _EQ046);
  _EQ046 =  data31 & !data32 & !_N016 &  _N017 &  _N018
         #  data21 & !data22 & !_N016 &  _N017 & !_N018
         #  data11 & !data12 & !_N016 & !_N017 &  _N018
         #  data01 & !data02 & !_N016 & !_N017 & !_N018
         #  data41 & !data42 &  _N016;

-- Node name is '|7447:65|~84~3' = '|7447:65|OD~3' 
-- Equation name is '_N052', type is buried 
-- synthesized logic cell 
_N052    = LCELL( _EQ047);
  _EQ047 = !data20 & !data22 & !data30 & !data32 & !data40 & !data42 &  _N017
         # !data00 & !data02 & !data10 & !data12 & !data40 & !data42 & !_N017
         # !data30 &  data31 & !_N016 &  _N017 &  _N018
         # !data20 &  data21 & !_N016 &  _N017 & !_N018
         # !data10 &  data11 & !_N016 & !_N017 &  _N018
         # !data30 & !data32 & !_N016 &  _N017 &  _N018
         # !data00 &  data01 & !_N016 & !_N017 & !_N018
         # !data10 & !data12 & !_N016 & !_N017 &  _N018;

-- Node name is '|7447:65|~84~4' = '|7447:65|OD~4' 
-- Equation name is '_N053', type is buried 
-- synthesized logic cell 
_N053    = LCELL( _EQ048);
  _EQ048 = !data20 & !data22 & !_N016 &  _N017 & !_N018
         # !data00 & !data02 & !_N016 & !_N017 & !_N018
         # !data40 &  data41 &  _N016
         # !data40 & !data42 &  _N016;

-- Node name is '|7447:65|~85~1' = '|7447:65|OE~1' 
-- Equation name is '_N045', type is buried 
-- synthesized logic cell 
_N045    = LCELL( _EQ049);
  _EQ049 = !data31 &  data32 & !_N016 &  _N017 &  _N018
         # !data11 &  data12 & !_N016 & !_N017 &  _N018
         # !data21 &  data22 & !_N016 &  _N017 & !_N018
         # !data01 &  data02 & !_N016 & !_N017 & !_N018
         # !data41 &  data42 &  _N016;

-- Node name is '|7447:65|~85~2' = '|7447:65|OE~2' 
-- Equation name is '_N051', type is buried 
-- synthesized logic cell 
_N051    = LCELL( _EQ050);
  _EQ050 =  data30 & !_N016 &  _N017 &  _N018
         #  data20 & !_N016 &  _N017 & !_N018
         #  data10 & !_N016 & !_N017 &  _N018
         #  data00 & !_N016 & !_N017 & !_N018
         #  data40 &  _N016;

-- Node name is '|7447:65|~86~1' = '|7447:65|OF~1' 
-- Equation name is '_N041', type is buried 
-- synthesized logic cell 
_N041    = LCELL( _EQ051);
  _EQ051 =  data30 & !data32 & !data33 & !_N016 &  _N017 &  _N018
         #  data20 & !data22 & !data23 & !_N016 &  _N017 & !_N018
         #  data10 & !data12 & !data13 & !_N016 & !_N017 &  _N018
         #  data00 & !data02 & !data03 & !_N016 & !_N017 & !_N018
         #  data30 &  data31 & !_N016 &  _N017 &  _N018
         #  data20 &  data21 & !_N016 &  _N017 & !_N018
         #  data10 &  data11 & !_N016 & !_N017 &  _N018
         #  data00 &  data01 & !_N016 & !_N017 & !_N018;

-- Node name is '|7447:65|~86~2' = '|7447:65|OF~2' 
-- Equation name is '_N043', type is buried 
-- synthesized logic cell 
_N043    = LCELL( _EQ052);
  _EQ052 =  data40 & !data42 & !data43 &  _N016
         #  data40 &  data41 &  _N016;

-- Node name is '|7447:65|~87~1' = '|7447:65|OG~1' 
-- Equation name is '_N044', type is buried 
-- synthesized logic cell 
_N044    = LCELL( _EQ053);
  _EQ053 = !data32 &  data33 & !_N016 &  _N017 &  _N018
         # !data30 &  data32 & !_N016 &  _N017 &  _N018
         # !data12 &  data13 & !_N016 & !_N017 &  _N018
         # !data22 &  data23 & !_N016 &  _N017 & !_N018
         # !data10 &  data12 & !_N016 & !_N017 &  _N018
         # !data20 &  data22 & !_N016 &  _N017 & !_N018
         # !data02 &  data03 & !_N016 & !_N017 & !_N018
         # !data00 &  data02 & !_N016 & !_N017 & !_N018;

-- Node name is '|7447:65|~87~2' = '|7447:65|OG~2' 
-- Equation name is '_N046', type is buried 
-- synthesized logic cell 
_N046    = LCELL( _EQ054);
  _EQ054 = !data42 &  data43 &  _N016
         # !data40 &  data42 &  _N016;

-- Node name is ':105' 
-- Equation name is '_N019', type is buried 
_N019    = DFF( _EQ055, GLOBAL( CLK),  VCC,  VCC);
  _EQ055 = !_N020 &  _N021 &  _N022 &  _N023 &  _N024 &  _N025 & !_N026 & 
             !_N028 &  _N029 &  _N030 &  _N031 &  _N032;



Project Informationc:\laboratorio\altro\esercitazioni2003\esp_fpga_2(cronometro)\pilota_display.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'CLASSIC' family

      MINIMIZATION                        = full
      SOFT_BUFFER_INSERTION               = on
      TURBO_BIT                           = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:01
   Logic Synthesizer                      00:00:07
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   --------------------------             --------
   Total Time                             00:00:09


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,172K
