Project Informationd:\laboratorio\altro\esercitazioni2003\esp_fpga_2(alu)\alu2.rpt

MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 12/03/2003 15:58:26

Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

alu2      EPF10K10TC144-4  10     9      0    0         0  %    51       8  %

User Pins:                 10     9      0  



Project Informationd:\laboratorio\altro\esercitazioni2003\esp_fpga_2(alu)\alu2.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

alu2@41                           a0
alu2@39                           a1
alu2@38                           a2
alu2@37                           a3
alu2@49                           b0
alu2@48                           b1
alu2@47                           b2
alu2@46                           b3
alu2@130                          parity
alu2@99                           res0
alu2@100                          res1
alu2@101                          res2
alu2@102                          res3
alu2@117                          res4
alu2@118                          res5
alu2@119                          res6
alu2@120                          res7
alu2@78                           sel0
alu2@79                           sel1


Project Informationd:\laboratorio\altro\esercitazioni2003\esp_fpga_2(alu)\alu2.rpt

** FILE HIERARCHY **



|mult:1|
|mult:1|lpm_mult:lpm_mult_component|
|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|
|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|
|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|
|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|
|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|
|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|
|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|
|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|altshift:result_ext_latency_ffs|
|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|altshift:carry_ext_latency_ffs|
|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|altshift:oflow_ext_latency_ffs|
|mult:1|lpm_mult:lpm_mult_component|altshift:external_latency_ffs|
|add4:2|
|add4:2|lpm_add_sub:lpm_add_sub_component|
|add4:2|lpm_add_sub:lpm_add_sub_component|addcore:adder|
|add4:2|lpm_add_sub:lpm_add_sub_component|altshift:result_ext_latency_ffs|
|add4:2|lpm_add_sub:lpm_add_sub_component|altshift:carry_ext_latency_ffs|
|add4:2|lpm_add_sub:lpm_add_sub_component|altshift:oflow_ext_latency_ffs|
|mux2:31|
|mux2:31|lpm_mux:lpm_mux_component|
|mux2:31|lpm_mux:lpm_mux_component|altshift:external_latency_ffs|
|mux2:31|lpm_mux:lpm_mux_component|muxlut:94|
|mux2:31|lpm_mux:lpm_mux_component|muxlut:112|
|mux2:31|lpm_mux:lpm_mux_component|muxlut:130|
|mux2:31|lpm_mux:lpm_mux_component|muxlut:148|
|mux2:31|lpm_mux:lpm_mux_component|muxlut:166|
|mux2:31|lpm_mux:lpm_mux_component|muxlut:184|
|mux2:31|lpm_mux:lpm_mux_component|muxlut:202|
|mux2:31|lpm_mux:lpm_mux_component|muxlut:220|
|and4:32|
|and4:32|lpm_and:lpm_and_component|
|or4:33|
|or4:33|lpm_or:lpm_or_component|
|xor_8:49|
|xor_8:49|lpm_xor:lpm_xor_component|


Device-Specific Information:d:\laboratorio\altro\esercitazioni2003\esp_fpga_2(alu)\alu2.rpt
alu2

***** Logic for device 'alu2' compiled without errors.




Device: EPF10K10TC144-4

FLEX 10K Configuration Scheme: Passive Serial

Device Options:
    User-Supplied Start-Up Clock               = OFF
    Auto-Restart Configuration on Frame Error  = OFF
    Release Clears Before Tri-States           = OFF
    Enable Chip_Wide Reset                     = OFF
    Enable Chip-Wide Output Enable             = OFF
    Enable INIT_DONE Output                    = OFF
    JTAG User Code                             = 7f
    MultiVolt I/O                              = OFF

                                                                                         
                                                                                         
                R R R R R   R R R R   R R R     R           R R         R   R R R R R R  
                E E E E E   E E E E   E E E     E           E E         E   E E E E E E  
                S S S S S   S S S S   S S S p   S G G G G V S S         S   S S S S S S  
                E E E E E G E E E E V E E E a G E N N N N C E E         E V E E E E E E  
                R R R R R N R R R R C R R R r N R D D D D C R R r r r r R C R R R R R R  
                V V V V V D V V V V C V V V i D V I I I I I V V e e e e V C V V V V V V  
                E E E E E I E E E E I E E E t I E N N N N N E E s s s s E I E E E E E E  
                D D D D D O D D D D O D D D y O D T T T T T D D 7 6 5 4 D O D D D D D D  
              --------------------------------------------------------------------------_ 
             / 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110   |_ 
            /    143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109    | 
      #TCK |  1                                                                         108 | ^DATA0 
^CONF_DONE |  2                                                                         107 | ^DCLK 
     ^nCEO |  3                                                                         106 | ^nCE 
      #TDO |  4                                                                         105 | #TDI 
     VCCIO |  5                                                                         104 | GNDIO 
    VCCINT |  6                                                                         103 | GNDINT 
  RESERVED |  7                                                                         102 | res3 
  RESERVED |  8                                                                         101 | res2 
  RESERVED |  9                                                                         100 | res1 
  RESERVED | 10                                                                          99 | res0 
  RESERVED | 11                                                                          98 | RESERVED 
  RESERVED | 12                                                                          97 | RESERVED 
  RESERVED | 13                                                                          96 | RESERVED 
  RESERVED | 14                                                                          95 | RESERVED 
     GNDIO | 15                                                                          94 | VCCIO 
    GNDINT | 16                                                                          93 | VCCINT 
  RESERVED | 17                                                                          92 | RESERVED 
  RESERVED | 18                                                                          91 | RESERVED 
  RESERVED | 19                             EPF10K10TC144-4                              90 | RESERVED 
  RESERVED | 20                                                                          89 | RESERVED 
  RESERVED | 21                                                                          88 | RESERVED 
  RESERVED | 22                                                                          87 | RESERVED 
  RESERVED | 23                                                                          86 | RESERVED 
     VCCIO | 24                                                                          85 | GNDIO 
    VCCINT | 25                                                                          84 | GNDINT 
  RESERVED | 26                                                                          83 | RESERVED 
  RESERVED | 27                                                                          82 | RESERVED 
  RESERVED | 28                                                                          81 | RESERVED 
  RESERVED | 29                                                                          80 | RESERVED 
  RESERVED | 30                                                                          79 | sel1 
  RESERVED | 31                                                                          78 | sel0 
  RESERVED | 32                                                                          77 | ^MSEL0 
  RESERVED | 33                                                                          76 | ^MSEL1 
      #TMS | 34                                                                          75 | VCCINT 
  ^nSTATUS | 35                                                                          74 | ^nCONFIG 
  RESERVED | 36                                                                          73 | RESERVED 
           |      38  40  42  44  46  48  50  52  54  56  58  60  62  64  66  68  70  72  _| 
            \   37  39  41  43  45  47  49  51  53  55  57  59  61  63  65  67  69  71   | 
             \--------------------------------------------------------------------------- 
                a a a G a R R R V b b b b G R V V G G G G G R R V R R R R G R R R R V R  
                3 2 1 N 0 E E E C 3 2 1 0 N E C C N N N N N E E C E E E E N E E E E C E  
                      D   S S S C         D S C C D D D D D S S C S S S S D S S S S C S  
                      I   E E E I         I E I I I I I I I E E I E E E E I E E E E I E  
                      O   R R R O         O R N N N N N N N R R O R R R R O R R R R O R  
                          V V V             V T T T T T T T V V   V V V V   V V V V   V  
                          E E E             E               E E   E E E E   E E E E   E  
                          D D D             D               D D   D D D D   D D D D   D  
                                                                                         
                                                                                         


N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.


Device-Specific Information:d:\laboratorio\altro\esercitazioni2003\esp_fpga_2(alu)\alu2.rpt
alu2

** RESOURCE USAGE **

Logic                Column       Row                                   
Array                Interconnect Interconnect         Clears/     External  
Block   Logic Cells  Driven       Driven       Clocks  Presets   Interconnect
A3       1/ 8( 12%)   0/ 8(  0%)   1/ 8( 12%)    0/2    0/2       2/22(  9%)   
A6       6/ 8( 75%)   0/ 8(  0%)   5/ 8( 62%)    0/2    0/2      13/22( 59%)   
A7       3/ 8( 37%)   2/ 8( 25%)   3/ 8( 37%)    0/2    0/2       6/22( 27%)   
A9       7/ 8( 87%)   1/ 8( 12%)   3/ 8( 37%)    0/2    0/2       8/22( 36%)   
A11      6/ 8( 75%)   1/ 8( 12%)   1/ 8( 12%)    0/2    0/2       7/22( 31%)   
A13      1/ 8( 12%)   1/ 8( 12%)   0/ 8(  0%)    0/2    0/2       4/22( 18%)   
C1       3/ 8( 37%)   3/ 8( 37%)   0/ 8(  0%)    0/2    0/2       6/22( 27%)   
C2       1/ 8( 12%)   1/ 8( 12%)   0/ 8(  0%)    0/2    0/2       3/22( 13%)   
C4       8/ 8(100%)   2/ 8( 25%)   2/ 8( 25%)    0/2    0/2       9/22( 40%)   
C5       7/ 8( 87%)   3/ 8( 37%)   0/ 8(  0%)    0/2    0/2      10/22( 45%)   
C10      7/ 8( 87%)   1/ 8( 12%)   2/ 8( 25%)    0/2    0/2       7/22( 31%)   
C12      1/ 8( 12%)   1/ 8( 12%)   0/ 8(  0%)    0/2    0/2       4/22( 18%)   


Embedded             Column       Row                                   
Array     Embedded   Interconnect Interconnect         Read/      External  
Block     Cells      Driven       Driven       Clocks  Write    Interconnect


Total dedicated input pins used:                 0/6      (  0%)
Total I/O pins used:                            19/96     ( 19%)
Total logic cells used:                         51/576    (  8%)
Total embedded cells used:                       0/24     (  0%)
Total EABs used:                                 0/3      (  0%)
Average fan-in:                                 3.52/4    ( 88%)
Total fan-in:                                 180/2304    (  7%)

Total input pins required:                      10
Total input I/O cell registers required:         0
Total output pins required:                      9
Total output I/O cell registers required:        0
Total buried I/O cell registers required:        0
Total bidirectional pins required:               0
Total reserved pins required                     0
Total logic cells required:                     51
Total flipflops required:                        0
Total packed registers required:                 0
Total logic cells in carry chains:               0
Total number of carry chains:                    0
Total logic cells in cascade chains:             0
Total number of cascade chains:                  0
Total single-pin Clock Enables required:         0
Total single-pin Output Enables required:        0

Synthesized logic cells:                        12/ 576   (  2%)

Logic Cell and Embedded Cell Counts

Column:  01  02  03  04  05  06  07  08  09  10  11  12  EA  13  14  15  16  17  18  19  20  21  22  23  24  Total(LC/EC)
 A:      0   0   1   0   0   6   3   0   7   0   6   0   0   1   0   0   0   0   0   0   0   0   0   0   0     24/0  
 B:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0      0/0  
 C:      3   1   0   8   7   0   0   0   0   7   0   1   0   0   0   0   0   0   0   0   0   0   0   0   0     27/0  

Total:   3   1   1   8   7   6   3   0   7   7   6   1   0   1   0   0   0   0   0   0   0   0   0   0   0     51/0  



Device-Specific Information:d:\laboratorio\altro\esercitazioni2003\esp_fpga_2(alu)\alu2.rpt
alu2

** INPUTS **

                                                    Fan-In    Fan-Out
 Pin     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
  41      -     -    -    20      INPUT                0    0    0    9  a0
  39      -     -    -    21      INPUT                0    0    0   10  a1
  38      -     -    -    22      INPUT                0    0    0   12  a2
  37      -     -    -    23      INPUT                0    0    0   12  a3
  49      -     -    -    14      INPUT                0    0    0    9  b0
  48      -     -    -    15      INPUT                0    0    0   13  b1
  47      -     -    -    16      INPUT                0    0    0   12  b2
  46      -     -    -    17      INPUT                0    0    0   11  b3
  78      -     -    C    --      INPUT                0    0    0   11  sel0
  79      -     -    C    --      INPUT                0    0    0    7  sel1


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable


Device-Specific Information:d:\laboratorio\altro\esercitazioni2003\esp_fpga_2(alu)\alu2.rpt
alu2

** OUTPUTS **

       Fed By Fed By                                Fan-In    Fan-Out
 Pin     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
 130      -     -    -    14     OUTPUT                0    1    0    0  parity
  99      -     -    A    --     OUTPUT                0    1    0    0  res0
 100      -     -    A    --     OUTPUT                0    1    0    0  res1
 101      -     -    A    --     OUTPUT                0    1    0    0  res2
 102      -     -    A    --     OUTPUT                0    1    0    0  res3
 117      -     -    -    06     OUTPUT                0    1    0    0  res4
 118      -     -    -    07     OUTPUT                0    1    0    0  res5
 119      -     -    -    08     OUTPUT                0    1    0    0  res6
 120      -     -    -    09     OUTPUT                0    1    0    0  res7


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable


Device-Specific Information:d:\laboratorio\altro\esercitazioni2003\esp_fpga_2(alu)\alu2.rpt
alu2

** BURIED LOGIC **

                                                    Fan-In    Fan-Out
 IOC     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
   -      8     -    C    04        OR2                4    0    0    2  |add4:2|lpm_add_sub:lpm_add_sub_component|addcore:adder|pcarry1
   -      1     -    C    04        OR2                2    1    0    2  |add4:2|lpm_add_sub:lpm_add_sub_component|addcore:adder|pcarry2
   -      6     -    C    05        OR2                2    1    0    1  |add4:2|lpm_add_sub:lpm_add_sub_component|addcore:adder|pcarry3
   -      6     -    A    03       AND2                2    0    0    2  |add4:2|lpm_add_sub:lpm_add_sub_component|addcore:adder|:61
   -      5     -    C    04        OR2                4    0    0    1  |add4:2|lpm_add_sub:lpm_add_sub_component|addcore:adder|:70
   -      3     -    C    05        OR2                2    2    0    3  |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:84
   -      1     -    A    11        OR2                2    2    0    2  |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:85
   -      4     -    A    09        OR2    s           4    0    0    1  |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|~86~1
   -      3     -    A    09        OR2                2    1    0    2  |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:86
   -      2     -    C    10       AND2                0    2    0    3  |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:92
   -      4     -    C    05        OR2                2    2    0    2  |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:165
   -      5     -    A    11        OR2                2    2    0    2  |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:166
   -      6     -    A    09       AND2    s           3    0    0    1  |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|~167~1
   -      7     -    A    09        OR2    s           3    1    0    1  |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|~167~2
   -      2     -    A    09        OR2                2    2    0    2  |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:167
   -      6     -    C    04        OR2                4    0    0    1  |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|:68
   -      7     -    C    10        OR2                2    2    0    2  |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|:77
   -      7     -    C    04        OR2    s           4    0    0    1  |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|~78~1
   -      4     -    C    04        OR2                2    1    0    2  |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|:78
   -      6     -    A    11        OR2                4    0    0    2  |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|:79
   -      6     -    C    10       AND2                4    0    0    2  |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|:84
   -      5     -    A    09       AND2                4    0    0    1  |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|:143
   -      3     -    C    10        OR2                2    2    0    2  |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|:149
   -      4     -    A    11       AND2    s           4    0    0    1  |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|~150~1
   -      3     -    A    11        OR2    s           4    0    0    1  |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|~150~2
   -      2     -    A    11        OR2                2    2    0    2  |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|:150
   -      5     -    C    05        OR2                0    4    0    2  |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry4
   -      3     -    A    07        OR2                0    3    0    2  |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry5
   -      7     -    C    05        OR2                0    4    0    1  |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|:127
   -      5     -    C    10       AND2                2    0    0    2  |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|decoder_node0_2
   -      4     -    C    10       AND2                2    0    0    2  |mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|decoder_node1_1
   -      3     -    A    06        OR2                4    0    1    1  |mux2:31|lpm_mux:lpm_mux_component|muxlut:94|result_node
   -      2     -    A    06        OR2                1    2    1    1  |mux2:31|lpm_mux:lpm_mux_component|muxlut:112|result_node
   -      2     -    C    04        OR2                2    2    0    1  |mux2:31|lpm_mux:lpm_mux_component|muxlut:112|:46
   -      3     -    C    01        OR2    s           3    0    0    1  |mux2:31|lpm_mux:lpm_mux_component|muxlut:112|~51~1
   -      1     -    A    06        OR2                1    3    1    1  |mux2:31|lpm_mux:lpm_mux_component|muxlut:130|result_node
   -      1     -    C    10        OR2                1    2    0    1  |mux2:31|lpm_mux:lpm_mux_component|muxlut:130|:41
   -      3     -    C    04        OR2                3    1    0    1  |mux2:31|lpm_mux:lpm_mux_component|muxlut:130|:45
   -      3     -    C    02        OR2    s           3    0    0    1  |mux2:31|lpm_mux:lpm_mux_component|muxlut:130|~51~1
   -      4     -    A    06        OR2                1    3    1    1  |mux2:31|lpm_mux:lpm_mux_component|muxlut:148|result_node
   -      2     -    C    05        OR2                1    2    0    1  |mux2:31|lpm_mux:lpm_mux_component|muxlut:148|:41
   -      4     -    C    12        OR2                3    1    0    1  |mux2:31|lpm_mux:lpm_mux_component|muxlut:148|:45
   -      5     -    C    01        OR2    s           3    0    0    1  |mux2:31|lpm_mux:lpm_mux_component|muxlut:148|~51~1
   -      1     -    C    05        OR2                2    2    1    1  |mux2:31|lpm_mux:lpm_mux_component|muxlut:166|result_node
   -      2     -    A    07        OR2                0    4    1    1  |mux2:31|lpm_mux:lpm_mux_component|muxlut:184|result_node
   -      1     -    A    07        OR2                0    4    1    1  |mux2:31|lpm_mux:lpm_mux_component|muxlut:202|result_node
   -      1     -    A    09        OR2                0    4    1    1  |mux2:31|lpm_mux:lpm_mux_component|muxlut:220|result_node
   -      2     -    C    01       AND2    s           2    0    0    3  |mux2:31|lpm_mux:lpm_mux_component|muxlut:220|result_node~1
   -      6     -    A    06        OR2    s           0    3    0    1  |xor_8:49|lpm_xor:lpm_xor_component|xor_cascade0_7~1
   -      5     -    A    06        OR2    s           0    3    0    1  |xor_8:49|lpm_xor:lpm_xor_component|xor_cascade0_7~2
   -      1     -    A    13        OR2                0    4    1    0  |xor_8:49|lpm_xor:lpm_xor_component|xor_cascade0_7


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register


Device-Specific Information:d:\laboratorio\altro\esercitazioni2003\esp_fpga_2(alu)\alu2.rpt
alu2

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:      12/ 96( 12%)    22/ 48( 45%)     0/ 48(  0%)    0/16(  0%)      4/16( 25%)     0/16(  0%)
B:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
C:      10/ 96( 10%)     5/ 48( 10%)     0/ 48(  0%)    2/16( 12%)      0/16(  0%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      4/24( 16%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      2/24(  8%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      3/24( 12%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
07:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
08:      2/24(  8%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
09:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
10:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      2/24(  8%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      2/24(  8%)     1/4( 25%)      1/4( 25%)       0/4(  0%)
15:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
16:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
17:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
21:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
22:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
23:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
24:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:d:\laboratorio\altro\esercitazioni2003\esp_fpga_2(alu)\alu2.rpt
alu2

** EQUATIONS **

a0       : INPUT;
a1       : INPUT;
a2       : INPUT;
a3       : INPUT;
b0       : INPUT;
b1       : INPUT;
b2       : INPUT;
b3       : INPUT;
sel0     : INPUT;
sel1     : INPUT;

-- Node name is 'parity' 
-- Equation name is 'parity', type is output 
parity   =  _LC1_A13;

-- Node name is 'res0' 
-- Equation name is 'res0', type is output 
res0     =  _LC3_A6;

-- Node name is 'res1' 
-- Equation name is 'res1', type is output 
res1     =  _LC2_A6;

-- Node name is 'res2' 
-- Equation name is 'res2', type is output 
res2     =  _LC1_A6;

-- Node name is 'res3' 
-- Equation name is 'res3', type is output 
res3     =  _LC4_A6;

-- Node name is 'res4' 
-- Equation name is 'res4', type is output 
res4     =  _LC1_C5;

-- Node name is 'res5' 
-- Equation name is 'res5', type is output 
res5     =  _LC2_A7;

-- Node name is 'res6' 
-- Equation name is 'res6', type is output 
res6     =  _LC1_A7;

-- Node name is 'res7' 
-- Equation name is 'res7', type is output 
res7     =  _LC1_A9;

-- Node name is '|add4:2|lpm_add_sub:lpm_add_sub_component|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC8_C4', type is buried 
_LC8_C4  = LCELL( _EQ001);
  _EQ001 =  a1 &  b1
         #  a0 &  a1 &  b0
         #  a0 &  b0 &  b1;

-- Node name is '|add4:2|lpm_add_sub:lpm_add_sub_component|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC1_C4', type is buried 
_LC1_C4  = LCELL( _EQ002);
  _EQ002 =  a2 &  b2
         #  a2 &  _LC8_C4
         #  b2 &  _LC8_C4;

-- Node name is '|add4:2|lpm_add_sub:lpm_add_sub_component|addcore:adder|pcarry3' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC6_C5', type is buried 
_LC6_C5  = LCELL( _EQ003);
  _EQ003 =  a3 &  b3
         #  b3 &  _LC1_C4
         #  a3 &  _LC1_C4;

-- Node name is '|add4:2|lpm_add_sub:lpm_add_sub_component|addcore:adder|:61' from file "addcore.tdf" line 312, column 28
-- Equation name is '_LC6_A3', type is buried 
_LC6_A3  = LCELL( _EQ004);
  _EQ004 =  a3 &  b3;

-- Node name is '|add4:2|lpm_add_sub:lpm_add_sub_component|addcore:adder|:70' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC5_C4', type is buried 
_LC5_C4  = LCELL( _EQ005);
  _EQ005 =  a0 &  a1 &  b0 &  b1
         #  a0 & !a1 &  b0 & !b1
         # !a0 &  a1 & !b1
         #  a1 & !b0 & !b1
         # !a0 & !a1 &  b1
         # !a1 & !b0 &  b1;

-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:84' from file "csa_cell.tdf" line 22, column 38
-- Equation name is '_LC3_C5', type is buried 
_LC3_C5  = LCELL( _EQ006);
  _EQ006 =  a0 &  b3 & !_LC3_C10 & !_LC4_C4
         # !a0 &  _LC3_C10 & !_LC4_C4
         # !b3 &  _LC3_C10 & !_LC4_C4
         #  a0 &  b3 &  _LC3_C10 &  _LC4_C4
         # !a0 & !_LC3_C10 &  _LC4_C4
         # !b3 & !_LC3_C10 &  _LC4_C4;

-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:85' from file "csa_cell.tdf" line 22, column 38
-- Equation name is '_LC1_A11', type is buried 
_LC1_A11 = LCELL( _EQ007);
  _EQ007 =  a1 &  b3 & !_LC2_A11 & !_LC6_A11
         # !a1 & !_LC2_A11 &  _LC6_A11
         # !b3 & !_LC2_A11 &  _LC6_A11
         #  a1 &  b3 &  _LC2_A11 &  _LC6_A11
         # !a1 &  _LC2_A11 & !_LC6_A11
         # !b3 &  _LC2_A11 & !_LC6_A11;

-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|~86~1' from file "csa_cell.tdf" line 22, column 38
-- Equation name is '_LC4_A9', type is buried 
-- synthesized logic cell 
_LC4_A9  = LCELL( _EQ008);
  _EQ008 = !a2 &  a3 &  b2
         #  a3 & !b1 &  b2;

-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:86' from file "csa_cell.tdf" line 22, column 38
-- Equation name is '_LC3_A9', type is buried 
_LC3_A9  = LCELL( _EQ009);
  _EQ009 =  a2 &  b3 & !_LC4_A9
         # !a2 &  _LC4_A9
         # !b3 &  _LC4_A9;

-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:92' from file "csa_cell.tdf" line 23, column 27
-- Equation name is '_LC2_C10', type is buried 
_LC2_C10 = LCELL( _EQ010);
  _EQ010 =  _LC6_C10 &  _LC7_C10;

-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:165' from file "csa_cell.tdf" line 24, column 44
-- Equation name is '_LC4_C5', type is buried 
_LC4_C5  = LCELL( _EQ011);
  _EQ011 =  _LC3_C10 &  _LC4_C4
         #  a0 &  b3 &  _LC3_C10
         #  a0 &  b3 &  _LC4_C4;

-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:166' from file "csa_cell.tdf" line 24, column 44
-- Equation name is '_LC5_A11', type is buried 
_LC5_A11 = LCELL( _EQ012);
  _EQ012 =  _LC2_A11 &  _LC6_A11
         #  a1 &  b3 &  _LC6_A11
         #  a1 &  b3 &  _LC2_A11;

-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|~167~1' from file "csa_cell.tdf" line 24, column 44
-- Equation name is '_LC6_A9', type is buried 
-- synthesized logic cell 
_LC6_A9  = LCELL( _EQ013);
  _EQ013 =  a2 & !b1 &  b3;

-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|~167~2' from file "csa_cell.tdf" line 24, column 44
-- Equation name is '_LC7_A9', type is buried 
-- synthesized logic cell 
_LC7_A9  = LCELL( _EQ014);
  _EQ014 =  b3 &  _LC5_A9
         #  a3 &  b2 &  _LC5_A9;

-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:167' from file "csa_cell.tdf" line 24, column 44
-- Equation name is '_LC2_A9', type is buried 
_LC2_A9  = LCELL( _EQ015);
  _EQ015 =  a3 &  b2 &  _LC6_A9
         #  _LC7_A9;

-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|:68' from file "csa_cell.tdf" line 22, column 26
-- Equation name is '_LC6_C4', type is buried 
_LC6_C4  = LCELL( _EQ016);
  _EQ016 =  a0 & !a1 &  b1
         #  a0 & !b0 &  b1
         # !a0 &  a1 &  b0
         #  a1 &  b0 & !b1;

-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|:77' from file "csa_cell.tdf" line 22, column 38
-- Equation name is '_LC7_C10', type is buried 
_LC7_C10 = LCELL( _EQ017);
  _EQ017 =  a0 &  b2 & !_LC4_C10 & !_LC5_C10
         # !a0 & !_LC4_C10 &  _LC5_C10
         # !b2 & !_LC4_C10 &  _LC5_C10
         #  a0 &  b2 &  _LC4_C10 &  _LC5_C10
         # !a0 &  _LC4_C10 & !_LC5_C10
         # !b2 &  _LC4_C10 & !_LC5_C10;

-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|~78~1' from file "csa_cell.tdf" line 22, column 38
-- Equation name is '_LC7_C4', type is buried 
-- synthesized logic cell 
_LC7_C4  = LCELL( _EQ018);
  _EQ018 =  a1 & !b0 &  b2
         #  a1 & !a3 &  b2
         # !a1 &  a3 &  b0
         #  a3 &  b0 & !b2;

-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|:78' from file "csa_cell.tdf" line 22, column 38
-- Equation name is '_LC4_C4', type is buried 
_LC4_C4  = LCELL( _EQ019);
  _EQ019 = !a2 &  _LC7_C4
         # !b1 &  _LC7_C4
         #  a2 &  b1 & !_LC7_C4;

-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|:79' from file "csa_cell.tdf" line 22, column 38
-- Equation name is '_LC6_A11', type is buried 
_LC6_A11 = LCELL( _EQ020);
  _EQ020 =  a2 & !b1 &  b2
         #  a2 & !a3 &  b2
         # !a2 &  a3 &  b1
         #  a3 &  b1 & !b2;

-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|:84' from file "csa_cell.tdf" line 23, column 27
-- Equation name is '_LC6_C10', type is buried 
_LC6_C10 = LCELL( _EQ021);
  _EQ021 =  a0 &  a1 &  b0 &  b1;

-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|:143' from file "csa_cell.tdf" line 25, column 31
-- Equation name is '_LC5_A9', type is buried 
_LC5_A9  = LCELL( _EQ022);
  _EQ022 =  a2 &  a3 &  b1 &  b2;

-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|:149' from file "csa_cell.tdf" line 24, column 44
-- Equation name is '_LC3_C10', type is buried 
_LC3_C10 = LCELL( _EQ023);
  _EQ023 =  _LC4_C10 &  _LC5_C10
         #  a0 &  b2 &  _LC5_C10
         #  a0 &  b2 &  _LC4_C10;

-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|~150~1' from file "csa_cell.tdf" line 24, column 44
-- Equation name is '_LC4_A11', type is buried 
-- synthesized logic cell 
_LC4_A11 = LCELL( _EQ024);
  _EQ024 =  a2 &  a3 &  b0 &  b1;

-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|~150~2' from file "csa_cell.tdf" line 24, column 44
-- Equation name is '_LC3_A11', type is buried 
-- synthesized logic cell 
_LC3_A11 = LCELL( _EQ025);
  _EQ025 =  a3 &  b0
         #  a2 &  b1;

-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|csa_cell:adder0|:150' from file "csa_cell.tdf" line 24, column 44
-- Equation name is '_LC2_A11', type is buried 
_LC2_A11 = LCELL( _EQ026);
  _EQ026 =  _LC4_A11
         #  a1 &  b2 &  _LC3_A11;

-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry4' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC5_C5', type is buried 
_LC5_C5  = LCELL( _EQ027);
  _EQ027 =  _LC2_C10 &  _LC3_C5 &  _LC4_C5
         #  _LC1_A11 &  _LC2_C10 &  _LC3_C5
         #  _LC1_A11 &  _LC4_C5;

-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry5' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC3_A7', type is buried 
_LC3_A7  = LCELL( _EQ028);
  _EQ028 =  _LC5_A11 &  _LC5_C5
         #  _LC3_A9 &  _LC5_C5
         #  _LC3_A9 &  _LC5_A11;

-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|:127' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC7_C5', type is buried 
_LC7_C5  = LCELL( _EQ029);
  _EQ029 = !_LC1_A11 & !_LC3_C5 &  _LC4_C5
         #  _LC1_A11 & !_LC3_C5 & !_LC4_C5
         # !_LC1_A11 & !_LC2_C10 &  _LC4_C5
         #  _LC1_A11 & !_LC2_C10 & !_LC4_C5
         #  _LC1_A11 &  _LC2_C10 &  _LC3_C5 &  _LC4_C5
         # !_LC1_A11 &  _LC2_C10 &  _LC3_C5 & !_LC4_C5;

-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|decoder_node0_2' from file "multcore.tdf" line 781, column 38
-- Equation name is '_LC5_C10', type is buried 
_LC5_C10 = LCELL( _EQ030);
  _EQ030 =  a2 &  b0;

-- Node name is '|mult:1|lpm_mult:lpm_mult_component|multcore:mult_core|decoder_node1_1' from file "multcore.tdf" line 781, column 38
-- Equation name is '_LC4_C10', type is buried 
_LC4_C10 = LCELL( _EQ031);
  _EQ031 =  a1 &  b1;

-- Node name is '|mux2:31|lpm_mux:lpm_mux_component|muxlut:94|result_node' from file "muxlut.tdf" line 173, column 80
-- Equation name is '_LC3_A6', type is buried 
_LC3_A6  = LCELL( _EQ032);
  _EQ032 =  b0 & !sel0 & !sel1
         # !a0 &  b0 & !sel0
         #  a0 & !b0 & !sel0
         #  a0 &  b0 &  sel0;

-- Node name is '|mux2:31|lpm_mux:lpm_mux_component|muxlut:112|result_node' from file "muxlut.tdf" line 173, column 80
-- Equation name is '_LC2_A6', type is buried 
_LC2_A6  = LCELL( _EQ033);
  _EQ033 =  _LC2_C4 &  _LC3_C1
         #  _LC2_C4 &  sel1;

-- Node name is '|mux2:31|lpm_mux:lpm_mux_component|muxlut:112|:46' from file "muxlut.tdf" line 173, column 56
-- Equation name is '_LC2_C4', type is buried 
_LC2_C4  = LCELL( _EQ034);
  _EQ034 =  _LC5_C4 & !sel0
         #  _LC6_C4 &  sel0
         # !sel1;

-- Node name is '|mux2:31|lpm_mux:lpm_mux_component|muxlut:112|~51~1' from file "muxlut.tdf" line 174, column 50
-- Equation name is '_LC3_C1', type is buried 
-- synthesized logic cell 
_LC3_C1  = LCELL( _EQ035);
  _EQ035 =  a1 &  b1
         #  a1 & !sel0
         #  b1 & !sel0;

-- Node name is '|mux2:31|lpm_mux:lpm_mux_component|muxlut:130|result_node' from file "muxlut.tdf" line 173, column 80
-- Equation name is '_LC1_A6', type is buried 
_LC1_A6  = LCELL( _EQ036);
  _EQ036 =  _LC1_C10 &  _LC3_C2
         #  _LC3_C2 &  _LC3_C4
         #  _LC3_C2 & !sel1
         #  _LC1_C10 &  sel1
         #  _LC3_C4 &  sel1;

-- Node name is '|mux2:31|lpm_mux:lpm_mux_component|muxlut:130|:41' from file "muxlut.tdf" line 173, column 46
-- Equation name is '_LC1_C10', type is buried 
_LC1_C10 = LCELL( _EQ037);
  _EQ037 = !_LC6_C10 &  _LC7_C10 &  sel0
         #  _LC6_C10 & !_LC7_C10 &  sel0;

-- Node name is '|mux2:31|lpm_mux:lpm_mux_component|muxlut:130|:45' from file "muxlut.tdf" line 173, column 69
-- Equation name is '_LC3_C4', type is buried 
_LC3_C4  = LCELL( _EQ038);
  _EQ038 =  a2 & !b2 & !_LC8_C4 & !sel0
         # !a2 &  b2 & !_LC8_C4 & !sel0
         #  a2 &  b2 &  _LC8_C4 & !sel0
         # !a2 & !b2 &  _LC8_C4 & !sel0;

-- Node name is '|mux2:31|lpm_mux:lpm_mux_component|muxlut:130|~51~1' from file "muxlut.tdf" line 174, column 50
-- Equation name is '_LC3_C2', type is buried 
-- synthesized logic cell 
_LC3_C2  = LCELL( _EQ039);
  _EQ039 =  a2 &  b2
         #  a2 & !sel0
         #  b2 & !sel0;

-- Node name is '|mux2:31|lpm_mux:lpm_mux_component|muxlut:148|result_node' from file "muxlut.tdf" line 173, column 80
-- Equation name is '_LC4_A6', type is buried 
_LC4_A6  = LCELL( _EQ040);
  _EQ040 =  _LC2_C5 &  _LC5_C1
         #  _LC4_C12 &  _LC5_C1
         #  _LC5_C1 & !sel1
         #  _LC2_C5 &  sel1
         #  _LC4_C12 &  sel1;

-- Node name is '|mux2:31|lpm_mux:lpm_mux_component|muxlut:148|:41' from file "muxlut.tdf" line 173, column 46
-- Equation name is '_LC2_C5', type is buried 
_LC2_C5  = LCELL( _EQ041);
  _EQ041 = !_LC2_C10 &  _LC3_C5 &  sel0
         #  _LC2_C10 & !_LC3_C5 &  sel0;

-- Node name is '|mux2:31|lpm_mux:lpm_mux_component|muxlut:148|:45' from file "muxlut.tdf" line 173, column 69
-- Equation name is '_LC4_C12', type is buried 
_LC4_C12 = LCELL( _EQ042);
  _EQ042 =  a3 &  b3 &  _LC1_C4 & !sel0
         # !a3 & !b3 &  _LC1_C4 & !sel0
         # !a3 &  b3 & !_LC1_C4 & !sel0
         #  a3 & !b3 & !_LC1_C4 & !sel0;

-- Node name is '|mux2:31|lpm_mux:lpm_mux_component|muxlut:148|~51~1' from file "muxlut.tdf" line 174, column 50
-- Equation name is '_LC5_C1', type is buried 
-- synthesized logic cell 
_LC5_C1  = LCELL( _EQ043);
  _EQ043 =  a3 &  b3
         #  b3 & !sel0
         #  a3 & !sel0;

-- Node name is '|mux2:31|lpm_mux:lpm_mux_component|muxlut:166|result_node' from file "muxlut.tdf" line 173, column 80
-- Equation name is '_LC1_C5', type is buried 
_LC1_C5  = LCELL( _EQ044);
  _EQ044 =  _LC7_C5 &  sel0 &  sel1
         #  _LC6_C5 & !sel0 &  sel1;

-- Node name is '|mux2:31|lpm_mux:lpm_mux_component|muxlut:184|result_node' from file "muxlut.tdf" line 173, column 80
-- Equation name is '_LC2_A7', type is buried 
_LC2_A7  = LCELL( _EQ045);
  _EQ045 =  _LC2_C1 & !_LC3_A9 &  _LC5_A11 & !_LC5_C5
         #  _LC2_C1 &  _LC3_A9 & !_LC5_A11 & !_LC5_C5
         #  _LC2_C1 &  _LC3_A9 &  _LC5_A11 &  _LC5_C5
         #  _LC2_C1 & !_LC3_A9 & !_LC5_A11 &  _LC5_C5;

-- Node name is '|mux2:31|lpm_mux:lpm_mux_component|muxlut:202|result_node' from file "muxlut.tdf" line 173, column 80
-- Equation name is '_LC1_A7', type is buried 
_LC1_A7  = LCELL( _EQ046);
  _EQ046 = !_LC2_A9 &  _LC2_C1 & !_LC3_A7 &  _LC6_A3
         #  _LC2_A9 &  _LC2_C1 & !_LC3_A7 & !_LC6_A3
         #  _LC2_A9 &  _LC2_C1 &  _LC3_A7 &  _LC6_A3
         # !_LC2_A9 &  _LC2_C1 &  _LC3_A7 & !_LC6_A3;

-- Node name is '|mux2:31|lpm_mux:lpm_mux_component|muxlut:220|result_node' from file "muxlut.tdf" line 173, column 80
-- Equation name is '_LC1_A9', type is buried 
_LC1_A9  = LCELL( _EQ047);
  _EQ047 =  _LC2_C1 &  _LC3_A7 &  _LC6_A3
         #  _LC2_A9 &  _LC2_C1 &  _LC3_A7
         #  _LC2_A9 &  _LC2_C1 &  _LC6_A3;

-- Node name is '|mux2:31|lpm_mux:lpm_mux_component|muxlut:220|result_node~1' from file "muxlut.tdf" line 173, column 80
-- Equation name is '_LC2_C1', type is buried 
-- synthesized logic cell 
_LC2_C1  = LCELL( _EQ048);
  _EQ048 =  sel0 &  sel1;

-- Node name is '|xor_8:49|lpm_xor:lpm_xor_component|xor_cascade0_7~1' from file "lpm_xor.tdf" line 63, column 22
-- Equation name is '_LC6_A6', type is buried 
-- synthesized logic cell 
_LC6_A6  = LCELL( _EQ049);
  _EQ049 = !_LC1_A6 & !_LC2_A6 &  _LC3_A6
         # !_LC1_A6 &  _LC2_A6 & !_LC3_A6
         #  _LC1_A6 &  _LC2_A6 &  _LC3_A6
         #  _LC1_A6 & !_LC2_A6 & !_LC3_A6;

-- Node name is '|xor_8:49|lpm_xor:lpm_xor_component|xor_cascade0_7~2' from file "lpm_xor.tdf" line 63, column 22
-- Equation name is '_LC5_A6', type is buried 
-- synthesized logic cell 
_LC5_A6  = LCELL( _EQ050);
  _EQ050 = !_LC1_C5 & !_LC4_A6 &  _LC6_A6
         # !_LC1_C5 &  _LC4_A6 & !_LC6_A6
         #  _LC1_C5 &  _LC4_A6 &  _LC6_A6
         #  _LC1_C5 & !_LC4_A6 & !_LC6_A6;

-- Node name is '|xor_8:49|lpm_xor:lpm_xor_component|xor_cascade0_7' from file "lpm_xor.tdf" line 63, column 22
-- Equation name is '_LC1_A13', type is buried 
_LC1_A13 = LCELL( _EQ051);
  _EQ051 = !_LC1_A7 &  _LC1_A9 &  _LC2_A7 &  _LC5_A6
         #  _LC1_A7 &  _LC1_A9 &  _LC2_A7 & !_LC5_A6
         # !_LC1_A7 & !_LC1_A9 & !_LC2_A7 &  _LC5_A6
         #  _LC1_A7 & !_LC1_A9 & !_LC2_A7 & !_LC5_A6
         #  _LC1_A7 & !_LC1_A9 &  _LC2_A7 &  _LC5_A6
         # !_LC1_A7 & !_LC1_A9 &  _LC2_A7 & !_LC5_A6
         #  _LC1_A7 &  _LC1_A9 & !_LC2_A7 &  _LC5_A6
         # !_LC1_A7 &  _LC1_A9 & !_LC2_A7 & !_LC5_A6;



Project Informationd:\laboratorio\altro\esercitazioni2003\esp_fpga_2(alu)\alu2.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = off
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 13,024K
